Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.5 years of experience with RTL coding using Verilog/SystemVerilog.Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.Preferred qualifications:Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.Experience with SOC implementation standards and interfaces (e.g., AXI).Experience as a design lead or technical management of RTL engineers.Experience with scripting languages (e.g., Tcl, Python or Perl).Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
Minimum qualifications:
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