Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.15 years of experience in ASIC/SoC development with Verilog/SystemVerilog.Experience in micro-architecture and design of IPs and Subsystems.Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).Preferred qualifications:Experience with programming languages (e.g., Python, C/C++ or Perl).Experience in SoC designs and integration flows.Knowledge of processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.Knowledge of high performance and low power design techniques.
Minimum qualifications:
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