Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.Experience in logic design and debug with Design Verification (DV).Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).Preferred qualifications:Experience in scripting languages like Python or Perl.
Minimum qualifications:
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