Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.5 years of experience with IP Development and/or Integration.Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.Experience with scripting languages like Perl or Python.Preferred qualifications:Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Minimum qualifications:
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