Position:Senior PD Engineer/ MTS (member of technical staff)Job Description:Principal AccountabilitiesResponsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR FlowExecute the block level place and route assignments from Netlist through GDS flowPerform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .Work with design teams for closing CTS, IO timing, DFT timing.
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