Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.8 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.Experience capturing design specification in a temporal assertion language (e.g., SVA or PSL).Preferred qualifications:Master’s degree or PhD in Electrical Engineering or Computer Science.Experience with scripting languages (e.g., Python).Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.Knowledge of formal verification algorithms.
Minimum qualifications:
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