Machine Learning Silicon IP Design Lead

Minimum qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.4 years of experience in leading IP/SoC design teams.Experience with ARM-based SoCs, interconnects, and ASIC methodology.Preferred qualifications:Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.15 years of experience with IP design for IPs in Machine learning, Neural Processors, Multimedia, or GPUs.Experience with methodologies for low power estimation, timing closure, and synthesis.Experience leading technical teams.Ability to drive a multi-generational roadmap for IP development.

Minimum qualifications:

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