Position:Design Verification Engineer (eInfochips Inc.)Job Description:What You’ll Be Doing:Understanding of Ethernet / project specifications.Writing Test plan and coverage plan.Write testcases/scenarios.Update existing testbench components like generators, drivers, and monitors.Debug existing tests failing in the regression.Work on Subsystem and system level verification.What We Are Looking For:At least 8+ years of experience in UVM.At least 8+ years of experience in System Verilog HVL and C++/C.Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.Proficient in SVTB/UVM, C++ testbench.Proficient in debug and assertions coding.Verification closure with team.Make/Perl/Python/ any script.Any protocol experience is fine.
Position:Design Verification Engineer (eInfochips Inc.)Job Description:What You’ll Be Doing:
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